The increasing performance requirements of artificial intelligence processors are pushing traditional memory architectures toward their limits in terms of bandwidth and power consumption. The roadmap presented by Sangwook Han of Samsung’s Memory Business Unit Design Team highlights the redesign of the HBM base layer using advanced logic processes. With this approach, the company aims to eliminate memory bottlenecks by transforming the base layer, which serves standard interface functions, into an active processor component.
Samsung’s strategy consists of three fundamental stages. The first stage focuses on reclaiming processor area. By moving the memory controller to the base layer and using compressed physical-layer designs, savings of 5 to 10 percent are achieved in the main processor area. Its contribution to performance, meanwhile, comes in the form of an increase of 10 to 20 percent. Heat Path Block technology, developed to control thermal hotspots, reduces peak temperatures by more than 35 percent.
The second stage focuses on expanding functional scope. Advanced fault-detection sensors, on-chip test mechanisms and direct memory expansion capabilities are incorporated into the architecture as part of this effort. This minimizes data movement while also reducing overall system power consumption. In the third and final stage, Samsung is moving to a vertical 3D integration structure called zHBM. The manufacturing achievements detailed in our report, Samsung achieves 80 percent yield rate in HBM4 memory production, form the foundation of this advanced layered architecture.
zHBM technology completely eliminates the need for a conventional 2.5D silicon interposer. Since the memory layers are vertically stacked directly on top of the graphics processor or AI accelerator, the data transmission distance is reduced to a minimum. According to the company’s technical data, zHBM provides 230 percent higher memory bandwidth than standard HBM4E solutions while reducing memory power consumption by 70 percent.
This architecture reduces the energy required per bit for data transmission to 0.5 picojoules while providing up to 100 Watts in power savings for each memory module. Gains in thermal and electrical efficiency create an additional power budget of 8.3 percent for the main processor. Samsung continues its work on advanced packaging technologies such as wafer-on-wafer and hybrid cube bonding as part of its goal of achieving vertical integration.
Next-Generation Standards and Increased Capacity
In HBM4 solutions used in the industry, bandwidth per module exceeds 3 TB/s, while this figure rises to the 4 TB/s limit in the HBM4E standard. With the HBM5 generation, capacity is expected to exceed 60 GB and bandwidth to reach twice the current level. Samsung’s use of 4nm logic processes with the D1c architecture in HBM4 production represents the first concrete step toward the advanced integration of memory circuits and logic circuits.