In Ken Shirriff’s examination of the architecture and microcode of Intel’s 8087 FPU, the FSCALE instruction turned out to be far more complex than expected. This instruction, which scales values by powers of two, uses more than 140 microinstructions and three levels of subroutine calls to handle all cases.
The process is divided into steps such as loading values into registers, performing calculations, checking for errors, and managing the stack. The 8087’s implementations later contributed to the development of the IEEE 754 floating-point standard.
Why it matters
This detail shows that a floating-point instruction is handled inside the processor not as a single arithmetic operation, but as a layered process coordinating different tasks. The presence of error checking and stack management in the same flow as the calculations makes the role of microcode in organizing how the hardware operates visible. For this reason, the examination is relevant not only to those investigating the internal structure of older processors, but also to those tracing the contribution of x87 implementations to the development of the IEEE 754 floating-point standard. However, the current findings do not elaborate on which design decisions led to this contribution to the development of the standard; the open question is how and to which elements of the standard these implementations in the 8087 were reflected.
Background
Intel is not a new name in the FikirPilot archive: we have published 4 news articles mentioning this name in the last 90 days; the most recent is dated September 9, 2026.